While we are on this subject, this kernel change on the sourceforge#

Mon, 29 Jul 2002 17:54:28 +0000

 While we are on this subject, this kernel change on the sourceforge
 machine meant that I had to transfer my ppc testing laboratory to Dan's
 iMac. And I found another nasty surprise waiting for me there. On the SF
 RS/6000 PPC, the floating point modifications worked as expected, giving
 the right kind of exceptions in the right circumstances. On Dan's iMac:
 
 * (/ 1.0 0.0)
 
 1.0 ; should signal DIVIDE-BY-ZERO

(Christophe's email to sbcl-devel). So, somehow, I got nominated to look at it.

I haven't actually fixed it yet. The immediate problem is that it's not sufficient to twiddle the FPSCR to enable floating point traps: you also have to set two bits in MSR (which, incidentally, you can't directly, as it's a privileged register). That's not actually a major problem, because there's a neato glibc function called feenableexcept() that does this (strace suggests that it works by installing a signal handler for SIGUSR1 that frobs the on-stack MSR, then doing kill(getpid(), SIGUSR1)). What is a major problem is getting it to stay set, because it gets reset in signal handlers, and restored when the handler returns - which punts us back into last week's problem, that half of the time, we don't return from said handlers in any conventional kind of way. Um. More details here